The present invention relates to a method and an apparatus for detecting an IC defect by irradiating a charged particle bean to an IC which is not packaged, detecting amount of a secondary electron emission caused by the irradiation of a charged particle beam and obtaining data corresponding to the potential state of an irradiated spot.
An IC tester is used to test if an IC operates normally. Using an IC tester, an IC can be tested whether or not the IC operates normally for each pin basis. Therefore, in an IC which is determined as a defect IC, which pin does not work normally can be detected. However, a defect inside the package, i.e., which wiring portion of the semiconductor chip of the IC cannot be identified.
If a defect wiring portion can be located during a trial manufacturing stage prior to the mass production or in the case where the defect rate is unusually high even in the mass production stage, a cause of the defect can be identified, and a corrective action such as an improvement of the IC manufacturing processes can be taken.
In order to identify a defect portion in an IC, an IC defect analyzing apparatus utilizing a charged particle beam has been used. In this IC defect analyzing apparatus, a charged particle beam such as an electron beam is irradiated to a chip of an IC under test (DUT=Device Under Test hereinafter), and amount of a secondary electron emission from a wiring pattern portion formed on the IC chip is measured to know a potential of the wiring pattern. Also in the IC defect analyzing apparatus, the surface of the IC chip is scanned by a charged particle beam, and the potential state of the scanned area is acquired as a potential contrast image and displayed such that a low potential portion of the wiring pattern is displayed as white (amount of secondary electron emission is large) and a high potential portion is displayed as black (amount of secondary electron emission is small). Thus a defect portion can be identified from the potential state of a wiring pattern. Such a method for detecting an IC defect using a charged particle beam is shown in U.S. patent application No. 08/181,584 entitled "IC Analysis System and Electron Beam Probe System and Fault Isolation Method Therefor" filed on Jan. 14, 1994, (now U.S. Pat. No. 5,528,156) or U.S. patent application No. 08/337,230 entitled "Method and Apparatus for Forming a Potential Distribution Image of Semiconductor Integrated Circuit" filed on Nov. 7, 1994, now abandoned.
In the identification of an IC defect, a potential contrast image is acquired first for a non-defect IC. Then, this potential contrast image is compared with a potential contrast image acquired for a defect IC by human eyes to locate the mismatch portion between the two potential contrast images. This process does not take much time if number of potential contrast image data is small. However, a recent IC is a large scale IC and contains many logic circuits in it. Since these logic circuits mutually relate each other and test patterns are applied to the IC sequentially to obtain the outputs in the usual process, it is necessary to examine which wiring portion of the IC is in failure at which test pattern address of a series of the test patterns. Moreover, an IC surface area is approximately 10 times (or more) of the maximum area where a charged particle beam can scan by deflection in a general charged particle beam tester. Thus, it is necessary to partition the entire IC surface into many segments for acquiring potential contrast image data for all the segments. Therefor, it is almost impossible to identify a defect wiring and the associated test pattern by performing the comparisons of the potential contrast images by human eyes in a test pattern basis for entire IC surface.